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rev 2.0, may 12, 2008 page 1 of 14 2 400 west cesar chavez, austin, tx 78701 1+(512) 416 - 8500 1+(512) 416 - 9669 www.silabs.com sl23ep09 ? key features ? 10 to 220 mhz operating frequency range ? low output clock skew: 45ps - typ ? low output clock jitter: ? 50 ps - typ cycle -to - cycle jitter ? 20 ps - typ period jitter ? low part -to - part output skew: 90 ps - typ ? wide 2.5 v to 3.3 v power supply ra nge ? low power dissipation: ? 26 ma - max at 66 mhz and vdd=3.3 v ? 24 ma - max at 66 mhz and vdd=2.5v ? one input drives 9 outputs organized as 4+4+1 ? select mode to bypass pll or tri - state outputs ? spreadthru ? pll that allows use of sscg ? standard and high - drive options ? available in 16 - pin soic and tssop packages ? available in commercial and industrial grades applications ? printers, mfps and digital copiers ? pcs and work stations ? routers, switchers and servers ? dig ital embeded systems description the sl23ep09 is a low skew, low jitter and low power zero delay buffer (zdb) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. the product h as an on - chip pll which locks to the input clock at clkin and receives its feedback internally from the clkout pin. the sl23ep09 has two (2) clock driver banks each with four (4) clock outputs. these outputs are controlled by two (2) select input pins s1 a nd s2. when only four (4) outputs are needed, four (4) bank - b output clock buffers can be tri - stated to reduce power dissipation and jitter. the select inputs can also be used to tri - state both banks a and b or drive them directly from the input bypassing the pll and making the product behave like a non - zero delay buffer (nzdb). the high - drive version operates up to 220mhz and 200mhz at 3.3v and 2.5v power supplies respectively. benefits ? up to nine (9) distribution of input clock ? standard and high - dirive le vels to control impedance level, frequency range and emi ? low power dissipation, jitter and skew ? low cost block diagram low power and low jitter pll mux input selection decoding logic vdd gnd 2 2 s2 s1 clkin clkout clka 1 clka 2 clka 3 clka 4 clkb 1 clkb 2 clkb 3 clkb 4 low jitter and skew 10 to 220 mhz zero delay buffer (zdb)
rev 2.0, may 12, 2008 page 2 of 14 sl23ep09 pin configuration clka1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clkout clka4 clka3 vdd gnd clkb4 clkb3 s1 clkin clka2 vdd gnd clkb1 clkb2 s2 pin description 16- pin soic and tssop pin number pin name pin type pin description 1 clkin input reference frequency clock input. weak pull - down (250k ). 2 clka1 output buffered clock output, bank a. weak pull - down (250k). 3 clka2 output buffered clock output, bank a. weak pull - down (250k). 4 vdd power 3.3v or 2.5v power supply. 5 gnd power power ground. 6 clkb1 output buffered clock output , bank b. weak pull - down (250k). 7 clkb2 output buffered clock output, bank b. weak pull - down (250k). 8 s2 input select input, select pin s2. weak pull - up (250k). 9 s1 input select input, select pin s1. weak pull - up (250k). 10 clkb3 output buff ered clock output, bank b. weak pull - down (250k). 11 clkb4 output buffered clock output, bank b. weak pull - down (250k). 12 gnd power power ground. 13 vdd power 3.3v or 2.5v power supply. 14 clka3 output buffered clock output, bank a. weak pull - down (250k). 15 clka4 output buffered clock output, bank a. weak pull - down (250k). 16 clkout output buffered clock output, pll internal feedback out put. weak pull - down (250k).
rev 2.0, may 12, 2008 page 3 of 14 sl23ep09 general description the sl23ep09 is a low skew, low jitt er zero delay buffer with very low operating current. the product includes an on - chip high performance pll that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock d istribution. in addition to clkout that is used for internal pll feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). input and output frequency range the input and output frequency range is the same. but, it depends on vdd and drive levels as given in the below table 1. vdd(v) drive min(mhz) max(mhz) 3.3 high 10 220 3.3 std 10 200 2.5 high 10 180 2.5 std 10 167 table 1. input/output frequency range if the input clo ck frequenc y is dc (gnd to vdd) , this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to hi - z. the pll is shutdown to save power. in this shutdown state , the product draws less than 12 a supply current. spreadthru ? feature if a spread spectrum clock (ssc) were to be used as an input clock, the sl23ep09 is designed to pass the modulated spread spectrum clock (ssc) signal from its reference input to the output clocks. the same spread ch aracteristics at the input are passed through the pll and drivers without any degradation in spread percent (%), spread profile and modulation frequency select input control the sl23ep09 provides two (2) input select control pins called s1 and s2. this fe ature enables users to selects various states of output clock banks - a and bank - b, output source and pll shutdown features as shown in the table 2. the s1 (pin -9) and s2 (pin - 8) inputs include 2 50 k weak pull - up resistors to vd d. pll bypass mode if the s2 and s1 pins are logic high(1) and low(0 ) respectively, the on - chip pll is shutdown and bypassed, and all the nine output clocks bank a, bank b and clkout clocks are driven directly from the reference input clock. in this operation mode sl23e p09 works like a non - zdb fanout buffer . high and low - drive product options the sl23ep09 is offered with high - drive ? - 1h? and standard - drive ? - 1? options. these drive options enable the users to contro l load levels, frequency range and emi control. refer to the ac electrical tables for the details. skew and zero delay all outputs should drive the similar load to achieve output -to - output skew and input -to - output specifications given in the ac electric al tables. however, zero delay between input and outputs can be adjusted by changing the loading of clkout relative to the banks a and b clocks since clkout is the feedback to the pll. power supply range (vdd) the sl23ep09 is designed to operate in a wi d e power supply range from 2.3v (min) to 3.6 v (max). an internal on - chip voltage regulator is used to supply pll constant power supply of 1.8v, leading to a consistent and stable pll electrical performance in terms of skew, jitter and power dissipation. con tact sli for 1.8v power supply version zdb called sl23epl09.
rev 2.0, may 12, 2008 page 4 of 14 sl23ep09 s2 s1 clock a1 - a4 clock b1 - 4 clkout output source pll status 0 0 tri - state tri - state driven pll on 0 1 driven tri - state driven pll on 1 0 driven driven driven reference off 1 1 driven driv en driven pll on table 2. select input decoding 0 5 10 15 20 25 30 -30 -25 -20 -5 -10 -15 1500 1000 500 -500 -1500 -1000 0 output load difference: fbk load ? clka or clkb load (pf) clkin input to clka or clkb delay (ps) figure 1. clkin input to clk a and b delay (in terms of load difference between clkout and clk a and b)
rev 2.0, may 12, 2008 page 5 of 14 sl23ep09 absolute maximum ratings description condition min. max. unit sup ply voltage, vdd ? 0.5 4.6 v all inputs and outputs ? 0.5 vdd+0.5 v ambient operating temperature in operation, c - grade 0 70 c ambient operating temperature in operation, i - grade ? 40 85 c storage temperature no power is applied ? 65 150 c juncti on temperature in operation, power is applied ? 125 c soldering temperature ? 260 c esd rating (human body model) jedeccc22 - a114d -4 000 4000 v esd rating (change device model) jedeccc22 - c101c -1500 1500 v esd rating (machine model) jedeccc22 - a115d -200 200 v
rev 2.0, may 12, 2008 page 6 of 14 sl23ep09 operating conditions: unless otherwise s tated vdd=2.3 v t o 3.6 v and for b oth c and i grades symbol description condition min. max. unit vdd3.3 3.3v supply voltage 3.3v+/ - 10% 3.0 3.6 v vdd2.5 2.5v supply voltage 2.5v+/ - 10% 2.3 2.7 v ta operating temperature(ambient) commercial 0 70 c industrial ? 40 85 c cload load capacitance < 220 mhz, 3.3v with high drive ? 15 pf < 200 mhz, 3.3 v with standard drive ? 15 pf < 180 mhz, 2.5 v with high drive ? 15 pf < 167 mhz , 2.5v with standard drive ? 15 pf <200 mhz, 3.3v with high drive ? 22 pf <180 mhz, 3.3v with standard drive ? 22 pf <167 mhz, 2.5v with high drive ? 22 pf <134 mhz, 2.5v with standard drive ? 22 pf <133 mhz, 3.3v with high drive ? 30 pf <100 mhz, 3.3v with standard drive ? 30 pf <80 mhz, 2.5v with high drive ? 30 pf <67 mhz, 2.5v with standard drive ? 30 pf cin input capacitance s1, s2 and clkin pins ? 5 pf rpu/d pull - up and pull - down resistors pins - 12/3/6/7/8/9/10 /11/14/15/16 250k - typ 175 325 k clbw closed - loop bandwidth 3.3v, (typical) 1.2 mhz 2.5v, (typical) 0.8 mhz zout output impedance 3.3v, (typical), high drive 29 ? 3.3v, (typical), standard drive 41 ? 2.5v, (typical), high drive 37 ? 2.5v, (typical), standard drive 41 ?
rev 2.0, may 12, 2008 page 7 of 14 sl23ep09 dc electrical specifications (vdd=3.3v): unless o th erwise stated for both c and i g rades dc electrical specifications (vdd=2.5v): unless otherwise stated for b oth c and i grades symbol description condition min max uni t vdd supply voltage 2.3 2.7 v vil input low voltage ? 0.7 v vih input high voltage 1.7 v dd + 0.3 v iil input leakage current 0 rev 2.0, may 12, 2008 page 8 of 14 sl23ep09 ac electrical specifications (vdd=3.3v and 2.5v) notes: 1. for the given maximum loading conditions. see cl in operating conditions table. 2. parameter is guaranteed by design and characterization. not 100% tested in production. symbol description condition min typ max unit fmax maximum frequency (input=output ) [1] 3.3v high drive 10 ? 220 mhz 3.3v standard drive 10 ? 200 mhz 2.5v high drive 10 ? 180 mhz 2.5v standard drive 10 ? 167 mhz indc input duty cycle <135 mhz, vdd=3.3v 25 ? 75 % <135 mhz, vdd=2.5v 40 ? 60 % outdc output duty cycle <135 mhz, vdd=3.3v [2] 45 ? 55 % <135 mhz, vdd=2.5v 40 60 % tr/f3.3 rise, fall time (3.3v) (measured at: 0.8 to 2.0v) [2] high drive, cl = 15 pf, < 135 mhz ? ? 0.75 ns std drive, cl = 15 pf, < 170 mhz ? ? 1.5 ns high drive, cl = 22 pf, < 135 mhz ? ? 1.2 ns std drive, cl = 22 pf, < 135 mhz ? ? 1.6 ns high drive, cl = 30 pf, < 100 mhz ? ? 1.5 ns st d drive, cl = 30 pf, > 100 mhz ? ? 2 .5 ns tr/f2.5 rise, fall time (2.5) (measured at: 0.6 to 1.8v) [2] high drive, cl = 15 pf, <135 mhz ? ? 1.5 ns std drive, cl = 15 pf, < 135 mhz ? ? 2.5 ns high drive, cl = 22 pf, <135 mhz ? ? 1.3 ns high drive, cl = 30 pf, > 100 mhz ? ? 2.5 ns t1 output -to - output skew [9] (measured at vdd/2) all outputs cl=0, 3.3v supply, 2.5 power supply, standard drive ? 45 100 ps all outputs cl=0, 2.5v power supply, high drive ? ? 110 ps t2 de lay time, clkin rising edge to clkout rising edge (measured at vdd/2) [2] pll bypass mode 1.5 ? 4.4 ns pll enabled @ 3.3v ? 100 ? 100 ps pll enabled @2.5v ? 200 ? 200 ps t3 part -to - part skew [2] (measured at vdd/2) measured at vdd/2. an y output to any output, 3.3v supply ? ? 150 ps measured at vdd/2. any output to any output, 2.5v supply ? ? 300 ps
rev 2.0, may 12, 2008 page 9 of 14 sl23ep09 ac electrical specifications (vdd=3.3v and 2.5v) (cont.) notes: 3. typical jitter is measured at 3.3v or 2.5v, 30 c with all outputs driven into the maximum specified load. symbol description condition min typ max unit tpllock pll lock time[9] time from 90% of vdd to valid clocks on all the output clocks ? ? 1.0 ms ccj cycle -to - cycle jitter [2,3] 3.3v supply, >66 mhz, <15 pf , high drive ? 30 60 ps 3.3v supply, >66 mhz, < 15 pf, standard drive ? 50 185 ps 2.5v supply, >66 mhz, < 15 pf, high drive ? 7 0 150 ps 2.5v supply, >66 mhz, <15 pf, stan dard drive ? 100 250 ps 3.3v supply, >66 mhz, < 30 pf, high drive ? 50 350 ps 3.3 v supply, >66 mhz, <30 pf, standard drive ? 65 250 ps 2.5v supply, >66 mhz, <30 pf, high drive ? 75 430 ps s2:s1 = 1:0 mode, 3.3v, <15pf, high drive ? 15 40 ps s2:s1 = 1:0 mode, 3.3v, <15pf, standard drive ? 15 40 ps s2:s1 = 1:0 mode, 2.5v, <15pf, high drive ? 20 50 ps s2:s1 = 1:0 mode, 2.5v, <15pf, standard drive ? 20 50 ps ppj [2,3] peak period jitter 3.3v supply, > 100 mhz , <15 pf , standard drive ? 40 90 ps 3.3v supply, 66- 100 mhz, <15 pf , standard drive ? 50 95 ps 2.5v supply, 66- 100 mhz, < 15 pf, high drive ? 40 85 ps 2.5 v supply, >66 mhz, < 15 pf, standard drive ? 75 180 ps 2.5v supply, > 100 mhz , <15 pf, high drive ? 15 45 ps s2:s1 = 1:0 mode, 3.3v, <15pf, standard drive ? 25 60 ps s2:s1 = 1:0 mode, 3.3v, <15pf, high drive ? 25 60 ps s2:s1 = 1:0 mode, 2.5v, <15pf, standard drive ? 40 80 ps s2:s1 = 1:0 mode, 2.5v, <15p f, high drive ? 40 80 ps
rev 2.0, may 12, 2008 page 10 of 14 sl23ep09 external components & design considerations typical application schematic sl23ep09 cl cl cl 0.1f 0.1f clkin clkout clka1 clkb4 gnd gnd s1 s2 vdd vdd 1 4 13 9 8 5 12 11 2 16 vdd comments and recommendations decoupling capacitor: $ghfrxsolqjfdsdflwruri)pxvwehxvhgehwzhhq9''dqg966slqv3odfhwkhfdsdflwrurq the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the g nd via should be kept as short as possible. do not use vias between the decoupling capacitor and the vdd pin. series termination resistor : a series termination resistor is recommended if the distance between the output clocks and the load is over 1 ? inch. the nominal impedance of the clock outputs is given on the page 4. place the series termination resistors as close to the clock outputs as possible. zero delay and skew control: all outputs and clkin pins should be loaded with the same load to achieve ?ze ro delay? between the clkin and the outputs. the clkout pin is connected to clkin internally on - chip for feedback to pll, and sees an additional 2 pf load with respect to bank a and b clocks. for applications requiring zero input/output delay, the load at the all output pins including the clkout pin must be the same. if any delay adjustment is required, the capacitance at the clkout pin could be increased or decreased to increase or decrease the delay between bank a and b clocks and clkin. for minimum pin -to - pin skew, the external load at all the bank a and b clocks must be the same.
rev 2.0, may 12, 2008 page 11 of 14 sl23ep09 switching waveforms output vdd/2 vdd/2 output t 1 input vdd/2 vdd/2 clkout t 2 t 3 any output part 1 or 2 vdd/2 vdd/2 any output part 2 or 1 figure 2. output to output skew figure 3. input to output skew figure 4. part -to - part skew
rev 2.0, may 12, 2008 page 12 of 14 sl23ep09 package drawing and dimensions 16- lead tssop ( 4.4mm) 0 . 190 ( 0 . 007 ) 0 . 300 ( 0 . 012 ) 0 . 090 ( 0 . 003 ) 0 . 200 ( 0 . 008 ) 8 9 6 . 250 ( 0 . 246 ) 6 . 500 ( 0 . 256 ) 4 . 300 ( 0 . 169 ) 4 . 500 ( 0 . 177 ) 2 . 900 ( 0 . 114 ) 3 . 100 ( 0 . 122 ) 0 . 850 ( 0 . 033 ) 0 . 950 ( 0 . 037 ) 0 . 050 ( 0 . 002 ) 0 . 150 ( 0 . 006 ) 1 . 100 ( 0 . 043 ) max 0 . 076 ( 0 . 003 ) 0 to 8 0 . 500 ( 0 . 020 ) 0 . 700 ( 0 . 027 ) 0 . 650 ( 0 . 025 ) bsc gauge plane dimensions are in milimeters ( inches ). top line : ( min ) and bottom line : ( max ) pin - 1 id seating plane 1 16 0 . 650 ( 0 . 025 ) bsc **dimensions are in inches (millimeters) thermal characteristics parameter symbol condition min typ max unit therm al resistance junction to ambient ja still air - 105 - c/w ja 1m/s air flow - 95 - c/w ja 3m/s air flow - 90 - c/w thermal resistance junction to case jc independent of air flow - 35 - c/w
rev 2.0, may 12, 2008 page 13 of 14 sl23ep09 package drawing and dimensions (cont.) 8 0 . 150 ( 3 . 810 ) 0 . 157 ( 3 . 987 0 . 230 ( 5 . 842 ) 0 . 244 ( 6 . 197 ) 0 . 189 ( 4 . 800 ) 0 . 196 ( 4 . 978 ) 0 . 050 ( 1 . 270 ) bsc 0 . 004 ( 0 . 102 ) seating plane 0 . 004 ( 0 . 102 ) 0 . 0098 ( 0 . 249 ) 0 . 061 ( 1 . 549 ) 0 . 068 ( 1 . 727 ) 0 to 8 0 . 010 ( 0 . 2540 ) 0 . 016 ( 0 . 406 ) x 45 0 . 016 ( 0 . 406 ) 0 . 035 ( 0 . 889 ) 0 . 0075 ( 0 . 190 ) 0 . 0098 ( 0 . 249 ) pin - 1 id dimensions are in milimeters ( inches ). top line : ( min ) and bottom line : ( max ) 16 - lead soic ( 150 mil ) 1 9 16 0 . 0138 ( 0 . 350 ) 0 . 0192 ( 0 . 487 ) **dimensions are in inches (millimeters) thermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja still air - 80 - c/w ja 1m/s air flow - 74 - c/w ja 3m/s ai r flow - 71 - c/w thermal resistance junction to case jc independent of air flow - 44 - c/w
rev 2.0, may 12, 2008 page 14 of 14 sl23ep09 ordering information [4] ordering number marking shipping package package temperature sl23ep09zc -1 sl23ep09zc -1 tube 16- pin tssop 0 to 70c sl23ep09zc -1 t sl23ep09zc -1 tape and reel 16- pin tssop 0 to 70c sl23ep09zc - 1h sl23ep09zc - 1h tube 16 - pin tssop 0 to 70c sl23ep09zc - 1ht sl23ep09zc - 1h tape and reel 16 - pin tssop 0 to 70c sl23ep09zi - 1 sl23ep09zi - 1 tube 16 - pin tssop - 40 to 85c sl23ep09zi -1t sl23ep09 zi -1 tape and reel 16- pin tssop - 40 to 85c sl23ep09zi -1h sl23ep09zi -1h tube 16- pin tssop - 40 to 85c sl23ep09zi - 1ht sl23ep09zi - 1h tape and reel 16 - pin tssop - 40 to 85c sl23ep09sc - 1 sl23ep09sc - 1 tube 16 - pin soic 0 to 70c sl23ep09sc - 1t sl23ep09sc - 1 ta pe and reel 16 - pin soic 0 to 70c sl23ep09sc -1h sl23ep09sc -1h tube 16- pin soic 0 to 70c sl23ep09sc - 1ht sl23ep09sc -1h tape and reel 16- pin soic 0 to 70c sl23ep09si - 1 sl23ep09si - 1 tube 16 - pin soic - 40 to 85c sl23ep09si - 1t sl23ep09si - 1 tape and reel 16 - pin soic - 40 to 85c sl23ep09si - 1h sl23ep09si - 1h tube 16 - pin soic - 40 to 85c sl23ep09si - 1ht sl23ep09si - 1h tape and reel 16 - pin soic - 40 to 85c notes: 4. the sl23ep09 products are rohs compliant. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences re sulting from the use of informatio n included herein. additionally, silicon laboratories assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warrant y, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laborat ories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authoriz ed for use in applications intended to support or sustain life, or for any other application in which the fail ure of the silicon laboratories product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for a ny such unintended or unauthorized application, buyer shall indemnify and hold silico n laboratories harmless against all claims and damages.

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